I was talking with a major storage vendor today and they said they were sampling sub-20nm NAND chips with P/E cycles of 300 with a data retention period under a week at room temperatures. With those specifications these chips almost can’t get out of the factory with any life left in them.
On the other hand the only sub-20nm (19nm) NAND information I could find online were inside the new Toshiba THNSNF SSDs with toggle MLC NAND that guaranteed data retention of 3 months at 40°C. I could not find any published P/E cycle specifications for the NAND in their drive but presumably this is at most equivalent to their prior generation 24 nm NAND or at worse somewhere below that generations P/E cycles. (Of course, I couldn’t find P/E cycle specifications for that drive either but similar technology in other drives seems to offer native 3000 P/E cycles.)
Intel-Micron, SanDisk and others have all recently announced 20nm MLC NAND chips with a P/E cycles around 3K to 5K.
Nevertheless, as NAND chips go beyond their rated P/E cycle quantities, NAND bit errors increase. With a more powerful ECC algorithm in SSDs and NAND controllers, one can still correct the data coming off the NAND chips. However at some point beyond 24 bit ECC this probably becomes unsustainable. (See interesting post by NexGen on ECC capabilities as NAND die size shrinks).
Not sure how to bridge the gap between 3-5K P/E cycles and the 300 P/E cycles being seen by storage vendors above but this may be a function of prototype vs. production technology and possibly it had other characteristics they were interested in.
But given the declining endurance of NAND below 20nm, some industry players are investigating other solid state storage technologies to replace NAND, e.g., MRAM, FeRAM, PCM and ReRAM all of which are current contenders, at least from a research perspective.
ReRAM is starting to emerge in low power applications as a substitute for SRAM/DRAM, but it’s still early yet.
I haven’t heard much about FeRAM other than last year researchers at Purdue having invented a new non-destructive read FeRAM they call FeTRAM. Standard FeRAMs are already in commercial use, albeit in limited applications from Ramtron and others but density is still a hurdle and write performance is a problem.
Recently the PCM approach has heated up as PCM technology is now commercially available being released by Micro. Yes the technology has a long way to go to catch up with NAND densities (available at 45nm technology) but it’s yet another start down a technology pathway to build volume and research ways to reduce cost, increase density and generally improve the technology. In the mean time I hear it’s an order of magnitude faster than NAND.
Racetrack memory, a form of MRAM using wires to store multiple bits, isn’t standing still either. Last December, IBM announced they have demonstrated Racetrack memory chips in their labs. With this milestone IBM has shown how a complete Racetrack memory chip could be fabricated on a CMOS technology lines.
However, in the same press release from IBM on recent research results, they announced a new technique to construct CMOS compatible graphene devices on a chip. As we have previously reported, another approach to replacing standard NAND technology uses graphene transistors to replace the storage layer of NAND flash. Graphene NAND holds the promise of increasing density with much better endurance, retention and reliability than today’s NAND.
So as of today, NAND is still the king of solid state storage technologies but there are a number of princelings and other emerging pretenders, all vying for its throne of tomorrow.