MTJ’s everywhere

I attended a IEEE Magnetic’s Society Distinguished Lecture series on MTJ (magnetic tunnel junction) which technology has been under development since 1960. It turns out since about 2004, the TMR (tunneling magneto-resistance) read head based on MTJs has been the dominant technology used in HDDs for reading magnetic bits recorded on media. TMR is a magneto-resistance effect that occurs in a MTJ (magnetic tunneling junction) device.

And MTJ devices are also used in today’s MRAM devices, one of the contenders to replace flash (e.g. see our The end of NAND… post). Given that TLC-QLC-PLC (NAND) flash and NAND 3D layering (now @230+ layers, checkout the GreyBeards FMS2022 wrapup podcast) have taken off, that replacement seems way down the line, if ever. But MRAM has other uses.

Disk heads

An MTJ is a device with two ferromagnets (iron, magnetite, or similar metals which can be magnetized and magnetizable material) separated by a small insulator which exhibit a quantum tunneling. The tunnelers, in an MTJ are electrons and the tunneling occurs in the presence of a magnetic field (like bits in disk media) across the insulating material.

Depending on the magnetic field electron tunneling is more successful (low resistance) or less successful (high resistance) and this allows the reading of the magnetic fields (bits) on the (magnetic) recording material.

In the past all disk devices used GMR (giant magnetoresistence heads) which uses a different technique to sense magnetic fields on recording media. Suffice it to say here that GMR head’s had a limitation when miniaturized which TMR heads do not. And this (along with shrinking write heads) has allowed bit density, track density and disk capacity to skyrocket over the past few years with nothing apparently stopping it.

So MTJ and the TMR head is one of the critical technologies keeping disks the dominant form of data storage in the market today.


On the other hand MRAM devices have been around a long time but they are still mainly used in niche applications.

There are two types of MRAM devices based on the MTJ one is a Toggle MRAM which uses current pulses to write MTJ bits and the STT-MRAM which uses spin-transfer torque (STT) to write a bit. It turns out that electrons have a spin or angular momentum. And most current in use today have electrons with mixed up spins. That is ~50% of the electrons in a current spin one way and 50% the other.

But if one sends current through a thicker “fixed” magnetic layer device, one can create spin polarized currents. If one then sends this spin polarized current through another smaller “free” magnetic layer, its spin can be transferred to the device and by doing so can change its resistance or write a bit of data. Presumably reading can be done with less current using the same MTJ. So once again a magneto-resistance effect that is being measured which can be used to detect bit values and in this case write bit values.

There’s a new, faster form of MRAM called SOT-MRAM (spin-orbit torque) which uses a different write mechanism but operates similarly for reads.

It turns out the Toggle MRAM devices don’t work well when you shrink bit dimensions which is not a problem with STT-MRAM devices.

One can see on this slide that the space taken up by one bit in Toggle MRAM can be used to store 2 bytes (16 bits) worth of data.

The only problem with STT-MRAM is fabricating the pit pillars cannot be done with chemistry (lithography using photo resists which is how most semiconductors are made today) alone but rather requires a combination of lithography and Ion Beam Etching (IBE) or milling.

IBE is an optical-mechanical process that uses Ions (charged particles) directed at the device to blast away metals and other material surrounding a MRAM bit pillar. The debris from IBE creates even more problems and has to be carefully removed. The problem is that IBE doesn’t scale as easily as lithography processes.

However, the nice thing about MRAM is that it can both be used as a potential replacement for NAND flash and DRAM.

In a NAND flash applications, MRAM has an endurance over 1M write cycles and great bit retention of over 10yrs.

In addition unlike DRAM and NAND both of which hold data in capacitors, MRAM holds data in a magnetic effect. As such it’s less susceptible to radiation damage, present in space and reactors. As such, MRAM has found a niche market in Satellites and other extreme environments.

As for MRAM scaling, Everspin announced in December of 2018 a 28nm node fab process, 1Gb MRAM storage chip, still their highest capacity MRAM chip on their website. TSMC and others have roadmaps to take MRAM technology to 14nm/12nm node fab processes which should increase capacity by 2X or more.

In contrast, Micron just announced a 232 layer 3D TLC NAND chip that has a raw capacity of 1Tb using what they call a 1α node process. So today Everspin’s latest chip is 1000 times less dense than best in class 3D TLC NAND to be shipping soon.

I did ask at the IEEE Magnetics session if MRAM could be scaled vertically and the answer was yes, but they didn’t provide any more details.

The other thing that NAND has done was change from a single bit per cell (SLC) to three bits per cell (TLC) which has helped increase density. I suppose there’s nothing stopping MRAM from offering more than one bit per pillar which would help as well. But I didn’t even ask that one.


MRAM may one day overcome it’s IBE scaling and single bit/pillar constraints to become a more viable competitor to 3D NAND flash and DRAM, but it seems a long way off.

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